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1 ?2005 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 25092, rev. 01 15 volt digitally programmable potentiometer (dpp) with 128 taps and 2-wire interface cat5132 features single linear digitally programmable potentiometer 128 resistor taps end-to-end resistance of 10k ? ? ? ? ? , 50k ? ? ? ? ? & 100k ? ? ? ? ? potentiometer control and memory access via 2-wire interface (i 2 c-like) nonvolatile memory storage for wiper settings automatic recall of saved wiper setting at power up special increment/decrement instruction mode for automatic trimming adjustments v cc operation from 2.7 v to 5.5 v v+ (analog voltage supply) operation from +8 v to +15v standby current less than 15 a 100 year nonvolatile memory data retention 10-pin msop package operating temperature of -40?c to + 85?c applications lcd screen adjustment volume control mechanical potentiometer replacement gain adjustment line impedance matching vcom setting adjustments description the cat5132 is a high voltage digitally programmable potentiometer (dpp) integrated with eeprom memory and control logic to operate in a similar manner as a mechanical potentiometer. the dpp consists of a series of resistive elements connected between two externally accessible end points. the tap points between each resistive element are connected to the wiper output with cmos switches. a separate 7-bit control register (wcr) independently controls the wiper tap switches for the dpp. associated with the control register is a 7-bit nonvolatile memory data register (dr) used for storing wiper settings. writing to the wiper control register or the nonvolatile data register is via a 2-wire serial bus (i 2 c- like). on power-up, wcr is set to mid scale (1000000) and after the power supply becomes stable, the contents of the data register (dr) are transferred to the wiper control register (wcr) and the wiper is positioned to that location. the cat5132 comes with 2 voltage supply inputs: v cc , the digital supply voltage input and v+, an analog supply voltage input. these inputs allow the v+ to be as much as 10 volts higher than the v cc and allow the dpp terminal values to be as much as 15 volts above ground. the cat5132 can be used as a potentiometer or as a two-terminal variable resistor. it is intended for circuit level adjustments. it is supplied standard in the -40 c to +85 c industrial operating temperature range and offered in the 10-pin msop package. sda scl a0 a1 v cc control logic and address decode 128 tap position decode control 7-bit wiper control register (wcr) 7-bit nonvolatile memory register (dr) v+ r h 127 resistive elements r l r w 127 0 block diagram
cat5132 2 doc. no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice pin configuration sda gnd v cc a1 a0 1 2 3 4 5 10 9 8 7 6 scl v+ r l r w r h pin description n i p r e b m u n e m a nn o i t p i r c s e d 1a d sn i p a t a d l a i r e s l a n o i t c e r i d i b - t u p t u o / t u p n i a t a d l a i r e s s i h t . 2 3 1 5 t a c e h t f o t u o d n a o t n i a t a d r e f s n a r t o t d e s u r e h t o h t i w d ' r o e r i w e b n a c d n a o / i n i a r d - n e p o n a s i . s o / i ) r o t c e l l o c n e p o r o ( n i a r d - n e p o 2d n gd n u o r g 3v c c ) v 5 . 5 o t v 7 . 2 ( e g a t l o v y l p p u s l a t i g i d 41 ar o f s s e r d d a e v a l s t c e l e s o t t u p n i t c e l e s s s e r d d a . s u b e r i w - 2 50 ar o f s s e r d d a e v a l s t c e l e s o t t u p n i t c e l e s s s e r d d a . s u b e r i w - 2 6r h r e t e m o i t n e t o p e h t r o f l a n i m r e t e c n e r e f e r h g i h 7r w r e t e m o i t n e t o p e h t r o f l a n i m r e t r e p i w 8r l r e t e m o i t n e t o p e h t r o f l a n i m r e t e c n e r e f e r w o l 9+ vo t v 0 . 8 + ( r e t e m o i t n e t o p e h t r o f e g a t l o v y l p p u s g o l a n a ) v 0 . 5 1 0 1l c ss i h t . s u b l a i r e s e r i w - 2 e h t r o f t u p n i k c o l c s u b l a i r e s f o t u o d n a o t n i s r e f s n a r t a t a d l l a k c o l c o t d e s u s i k c o l c 2 3 1 5 t a c e h t msop 10-pin package package prefix device # suffix 5132 r -10 te13 product number tape & reel 2500 units/reel cat resistance company id r: msop z: msop (green with sn lead finish) zg: msop (green with nipd au lead finsh) -10: 10k ohms -50: 50k ohms -100: 100k ohms temperature range i = industrial (-40 c to 85 c) i notes: 1. the device used in the above example is a cat5132r-10te13 (msop, 10k ohms, tape & reel). 2. the industrial temperature range of -40 ? c to +85 ? c is standard on the above product. ordering information
cat5132 3 doc no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice recommended operating conditions v cc = +2.7v to +5.5v v+ = 8.0v to +15v operating temperature range: -40 ? c to +85 ? c comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. absolute maximum ratings temperature under bias....................-55 ? c to +125 ? c storage temperature ........................ -65 ? c to +150 ? c voltage on any sda, scl, a0 & a1 pins with respect to ground (1)(2) .............................. -2.0v to v cc + 2.0v voltage on r h , r l & r w pins with respect to ground .................................... -2.0v to v+ + 1.0v v cc with respect to ground ................... -2.0v to 7.0v v+ with respect to ground ................... -2.0v to 16.0v wiper current (10 sec) ...................................... +6ma lead soldering temperature (10 sec) .............. +300 ? c potentiometer characteristics (over recommended operating conditions unless otherwise stated.) notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. 3. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. 4. lsb = (r hm - r lm )/127; where r hm and r lm are the highest and lowest measured values on the wiper terminal. 5. n = 1, 2, ..., 127 l o b m y sr e t e m a r a ps n o i t i d n o c t s e t s t i m i l s t i n u n i mp y tx a m r t o p k 0 0 1 ( e c n a t s i s e r r e t e m o i t n e t o p ? )0 0 1k ? r t o p k 0 5 ( e c n a t s i s e r r e t e m o i t n e t o p ? )0 5k ? r t o p k 0 1 ( e c n a t s i s e r r e t e m o i t n e t o p ? )0 1k ? r l o t e c n a r e l o t e c n a t s i s e r r e t e m o i t n e t o p + 0 2% g n i t a r r e w o pc 5 20 5w m i w t n e r r u c r e p i w + 3a m r w e c n a t s i s e r r e p i w i w =+ v 2 1 = + v @ a m 10 70 5 1 ? i w =+ v 8 = + v @ a m 10 1 10 0 2 ? v m r e t r n o e g a t l o v w r , h r r o l v 5 1 o t v 8 = + v ; v 0 = d n gd n g+ vv s e rn o i t u l o s e r 8 7 . 0% a n i l y t i r a e n i l e t u l o s b a ) 2 ( r ) l a u t c a ( ) n ( w r - ) d e t c e p x e ( ) n ( w ) 5 ( + 1b s l ) 4 ( r n i l y t i r a e n i l e v i t a l e r ) 3 ( r ) 1 + n ( w r [ - ) n ( w ] b s l + ) 5 ( + 5 . 0b s l ) 4 ( c t t o p r r f o t n e i c i f f e o c e r u t a r e p m e t t o p ) 1 ( + 0 0 3c / m p p c t o i t a r t n e i c i f f e o c e r u t a r e p m e t c i r t e m o i t a r ) 1 ( 0 3c / m p p c h c / l c / w s e c n a t i c a p a c r e t e m o i t n e t o p ) 1 ( 5 2 / 0 1 / 0 1f p c fe s n o p s e r y c n e u q e r fr t o p k 0 5 = ? 4 . 0z h m
cat5132 4 doc. no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice d.c. electrical characteristics (over recommended operating conditions unless otherwise stated.) l o b m y sr e t e m a r a ps n o i t i d n o c t s e tn i mx a ms t i n u c o / i ) a d s ( e c n a t i c a p a c t u p t u o / t u p n iv o / i v 0 = ) 1 ( 8f p c n i ) l c s , 1 a , 0 a ( e c n a t i c a p a c t u p n iv n i v 0 = ) 1 ( 6f p capacitance t a = 25 ? c, f = 1.0mhz, v cc = 5.0v l o b m y sr e t e m a r a p ) 1 . g i f e e s ( v c c v 5 . 5 - 7 . 2 = s t i n u n i mx a m f l c s y c n e u q e r f k c o l c 0 0 4z h k t i ) 1 ( s t u p n i a d s & l c s t a t n a t s n o c e m i t n o i s s e r p p u s e s i o n 0 5s n t a a t u o k c a d n a t u o a t a d a d s o t w o l c l s 1s t f u b ) 1 ( t r a t s n a c n o i s s i m s n a r t w e n a e r o f e b e e r f e b t s u m s u b e h t e m i t2 . 1s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s6 . 0s t w o l d o i r e p w o l k c o l c2 . 1s t h g i h d o i r e p h g i h k c o l c6 . 0s t a t s : u s ) n o i t i d n o c t r a t s d e t a e p e r a r o f ( e m i t p u t e s n o i t i d n o c t r a t s6 . 0s t t a d : d h e m i t d l o h n i a t a d0s n t r ) 1 ( e m i t e s i r l c s d n a a d s 3 . 0s t f ) 1 ( e m i t l l a f l c s d n a a d s 0 0 3s n t o t s : u s e m i t p u t e s s n o i t i d n o c p o t s6 . 0s t h d e m i t d l o h t u o a t a d0 0 1s n a.c. characteristics notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tn i mx a ms t i n u i 1 c c t n e r r u c y l p p u s r e w o p ) d a e r / e t i r w e l i t a l o v ( f l c s , n e p o a d s , z h k 0 0 4 = v c c d n g = t u p n i , v 5 . 5 = 1a m i 2 c c t n e r r u c y l p p u s r e w o p ) e t i r w e l i t a l o v n o n ( f l c s , n e p o a d s , z h k 0 0 4 = v c c d n g = t u p n i , v 5 . 5 = 0 . 3a m i ) c c v ( b s v ( t n e r r u c y b d n a t s c c ) v 5 =v n i v r o d n g = c c v = a d s , c c 5a i ) + v ( b s t n e r r u c y b d n a t s + vv c c v 5 1 = + v , v 5 =0 1a i i l t n e r r u c e g a k a e l t u p n iv n i v o t d n g = c c 0 1a i o l t n e r r u c e g a k a e l t u p t u ov t u o v o t d n g = c c 0 1a v l i e g a t l o v w o l t u p n i1 -v c c 3 . 0 xv v h i e g a t l o v h g i h t u p n iv c c 7 . 0 xv c c 0 . 1 +v v 1 l o v ( e g a t l o v w o l t u p t u o c c ) 0 . 3 =i l o a m 3 =4 . 0v
cat5132 5 doc no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice power up timing (1)(2) l o b m y sr e t e m a r a pn i mx a ms t i n u t r u p n o i t a r e p o d a e r o t p u - r e w o p1s m t w u p n o i t a r e p o e t i r w o t p u - r e w o p1s m xdcp timing l o b m y sr e t e m a r a pn i mx a ms t i n u t o p r w e l b a t s y l p p u s r e w o p r e t f a e m i t e s n o p s e r r e p i w50 1s t l r w d e u s s i n o i t c u r t s n i r e t f a e m i t e s n o p s e r r e p i w50 1s l o b m y sr e t e m a r a pn i mx a ms t i n u t r w ) 2 . g i f e e s ( e m i t e l c y c e t i r w5s m write cycle limits the write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high and the device does not respond to its slave address. reliability characteristics notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. 2. t pur and t puw are the delays required from the time vcc is stable until the specified operation can be initiated. l o b m y sr e t e m a r a pd o h t e m t s e t e c n e r e f e rn i mx a ms t i n u n d n e ) 1 ( e c n a r u d n e3 3 0 1 d o h t e m t s e t , 3 8 8 - d t s - l i m0 0 0 , 0 0 1e t y b / s e l c y c t r d ) 1 ( n o i t n e t e r a t a d8 0 0 1 d o h t e m t s e t , 3 8 8 - d t s - l i m0 0 1s r a e y v p a z ) 1 ( y t i l i b i t p e c s u s d s e5 1 0 3 d o h t e m t s e t , 3 8 8 - d t s - l i m0 0 0 2s t l o v i h t l ) 1 ( p u - h c t a l7 1 d r a d n a t s c e d e j0 0 1a m typical performance characteristics resistance between r w and r l 0.000 2.000 4.000 6.000 8.000 10.000 12.000 0 163248648096112128 tap position r wl (kohm) vcc=2.7v; v+=8v vcc=5.5v; v+=15v icc2 (nv write) vs temperature 0 50 100 150 200 250 300 350 400 -50 -30 -10 10 30 50 70 90 110 130 temperature ( c) icc2 (ua) vcc = 2.7v vcc = 5.5v
cat5132 6 doc. no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice figure 2. write cycle timing t wr stop condition start condition address ack 8th bit byte n scl sda t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 1. bus timing typical performance characteristics (cont) absolute linearity error per tap position -1.000 -0.800 -0.600 -0.400 -0.200 0.000 0.200 0.400 0.600 0.800 1.000 0 163248648096112128 tap position a lin error (lsb) vcc=2.7v; v+=8v vcc=5.5v; v+=15v tamb = 25 c rtotal = 10k relative linearity error -0.500 -0.400 -0.300 -0.200 -0.100 0.000 0.100 0.200 0.300 0.400 0.500 0 163248648096112128 tap position r lin error (lsb) vcc=2.7v; v+=8v vcc=5.5v; v+=15v tamb = 25 c rtotal = 10k
cat5132 7 doc no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 4. acknowledge condition serial bus protocol the following defines the features of the 2-wire bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat5132 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat5132 monitors the sda and scl lines and will not respond until this condition is met (see fig. 3). stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition (see fig. 3). figure 3. start/stop condition start condition sda stop condition scl acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data (see fig. 4). the cat5132 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat5132 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat5132 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the cat5132 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address. if the cat5132 is still busy with the write operation, no ack will be returned. if the cat5132 has completed the write operation, an ack will be returned and the host can then proceed with the next instruction operation.
cat5132 8 doc. no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice figure 5. access register addressing using 3 bytes table 2. byte 1 slave address and instruction byte h 2 0 - s s e r d d a r aon i t c e l e s ) h 0 0 ( r d / ) h 0 8 ( r wc t s 0 1010000a0000 0 010a1000 0000a t s 0 1010000a0000 0 010a0000 0000a p s 1st byte 2nd byte 3rd byte stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb ack sp table 1. access control register device description access control register the volatile register wcr and the non-volatile register dr of cat5132 are accessed only by addressing the volatile access register ar first, using the 3 byte i 2 c interface for all read and write operations (see table 1). the first byte is the slave address/instruction byte (see details below). the second byte contains the address (02h) of the ar register. the data in the third byte controls which register wcr (80h) or dr (00h) is being addressed (see figure 5). slave address instruction byte description the first byte sent to the cat5132 from the master processor is called the slave/dpp address byte. the most significant five bits of the slave address are a device type identifier. these bits for the cat5132 are fixed at 01010 (refer to table 2). the next two bits, a1 and a0, are the internal slave address and must match the physical device address which is defined by the state of the a1 and a0 input pins to successfully address the cat5132. only the device with slave address matching the input byte will be accessed by the master. this allows up to 4 devices to reside on the same bus. the a1 and a0 inputs can be actively driven by cmos input signals or tied to v cc or ground. the last bit is the read/write bit and determines the function to be performed. if it is a 1 a read command is initiated and if it is a 0 a write is initiated. for the ar register only write is allowed. after the master sends a start condition and the slave address byte, the cat5132 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. slave address & instruction s a c k a c k s t o p p bus activity: master sda line s t a r t a c k fixed variable ar register address wcr/dr selection r e i f i t n e d i e p y t e c i v e ds s e r d d a e v a l s/ d a e r e t i r w 4 d i3 d i2 d i1 d i0 d i1 a0 a/ r w 01010xx x ) b s m ( ) b s l (
cat5132 9 doc no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice wiper control register (wcr) description the cat5132 contains a 7-bit wiper control register which is decoded to select one of the 128 switches along its resistor array. the wcr is a volatile register and is written with the contents of the nonvolatile data register (dr) on power-up. the wiper control register loses its contents when the cat5132 is powered-down. the contents of the wcr may be read or changed directly by the host using a read/write command after addressing the wcr (see table 1 to access wcr). since the cat5132 will only make use of the 7 lsb bits (the first data bit, or msb, is ignored) on write instructions and will always come back as a 0 on read commands. xxxxxxx ax ah 2 0 - s s e r d d a r t s 0 1010000a0000 0 010a1000 0000a p s 1st byte 2nd byte 3rd byte stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb ack wcr(80h) selection t s 0 1010000a0000 0 000 a p s slave address byte wcr address - 00h data byte stop ack ack start ack 111 a1 ah 2 0 - s s e r d d a r t s 0 1010000a0000 0 010a1000 0000 1st byte 2nd byte 3rd byte asp stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb ack wcr(80h) selection t s 0 1011000a0000 0 000 sp slave address byte wcr address - 00h increment (1) / decrement (0) bits stop ack ack start 0000 ah 2 0 - s s e r d d a r t s 0 1010000a0000 0 010a1000 0000 stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb ack wcr(80h) selection t s 0 1010000a0000 0 000 slave address byte wcr address - 00h ack start t s 0 1010001a0xxxx xxx slave address byte data byte start sp stop 1st byte 2nd byte 3rd byte asp a write operation (see table 3) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a stop condition. after each of the three bytes the cat5132 responds with an acknowledge. at this time the data is written only to volatile registers, then the device enters its standby state. an increment operation (see table 4) requires a start condition, followed by a valid increment address byte (01011), a valid address byte 00h. after each of the two bytes, the cat5132 responds with an acknowledge. at this time if the data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. once the stop is issued then the device enters its standby state with the wcr data as being the last inc/dec position. also, the wiper position does not roll over but is limited to min and max positions. a read operation (see table 5) requires a start condition, followed by a valid slave address byte for write, a valid address byte 00h, a second start and a second slave address byte for read. after each of the three bytes, the cat5132 responds with an acknowledge and then the device transmits the data byte. the master terminates the read operation by issuing a stop condition following the last bit of data byte. table 3. wcr write operation table 4. wcr increment/decrement operation table 5. wcr read operation
cat5132 10 doc. no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice data register (dr) the data register (dr) is a nonvolatile register and its contents are automatically written to the wiper control register (wcr) on power-up. it can be read at any time without effecting the value of the wcr. the dr, like the wcr, only stores the 7 lsb bits and will report the msb bit as a 0 . writing to the dr is performed in the same fashion as the wcr except that a time delay of up to 5ms is experienced while the nonvolatile store operation is being performed. during the internal non-volatile write cycle, the device ignores transitions at the sda and scl pins, and the sda output is at a high impedance state. the wcr is also written during a write to dr. after a dr write is complete the dr and wcr will contain the same wiper position. xxxxxxx ax ah 2 0 - s s e r d d a r t s 0 1010000a0000 0 010a0000 0000a p s stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb ack dr(00h) selection t s 0 1010000a0000 0 000 a p s slave address byte dr address - 00h data byte stop ack ack start ack 1st byte 2nd byte 3rd byte to write or read to the dr, first the access to dr is selected, see table 1 then the data is written or read using the following sequences. a write operation (see table 6) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a stop condition. after each of the three bytes the cat5132 responds with an acknowledge. at this time the data is written both to volatile and non-volatile registers, then the device enters its standby state. a read operation (see table 7) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a second start and a second slave address byte for read. after each of the three bytes the cat5132 responds with an acknowledge and then the device transmits the data byte. the master terminates the read operation by issuing a stop condition following the last bit of data byte. table 6. dr write operation table 7. dr read operation ah 2 0 - s s e r d d a r t s 0 1010000a0000 0 010a0000 0000 stop ack ack start id4 id3 id2 id1 id0 a1 a0 wb ack dr(00h) selection t s 0 1010000a0000 0 000 slave address byte dr address - 00h ack start t s 0 1010001a0xxxx xxx slave address byte data byte start sp stop 1st byte 2nd byte 3rd byte asp
cat5132 11 doc no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice potentiometer operation power-on the cat5132 is a 128-position, digital controlled potentiometer. at power-up the device turns on at the mid-point wiper location (64) until the wiper register can be loaded with the nonvolatile memory location previously stored in the device. after the nonvolatile memory data is loaded into the wiper register the wiper location will change to the previously stored wiper position. the end-to-end nominal resistance of the potentiometer has 128 contact points linearly distributed across the total resistor. each of these contact points is addressed by the 7 bit wiper register which is decoded to select one of these 128 contact points. each contact point generates a linear resistive value between the 0 position and the 127 position. these values can be determined by dividing the end-to-end value of the potentiometer by 127. in the case of the 10k ? potentiometer~79 ? is the resistance between each wiper position. however in addition to the ~79 ? for each resistive segment of the potentiometer, a wiper resistance offset must be considered. table 8 shows the effect of this value and how it would appear on the wiper terminal. this offset will appear in each of the cat5132 end-to- end resistance values in the same way as the 10k ? example. however resistance between each wiper position for the 50k ? version will be ~395 ? and for the 100k ? version will be ~790 ? . table 8. potentiometer resistance and wiper resistance offset effects n o i t i s o p r l a c i p y t w r o t l r o f e c n a t s i s e r k 0 1 ? ? ? ? ? p p d 0 00 7 ? r o0 ? 0 7 + ? 1 09 4 1 ? r o9 7 ? 0 7 + ? 3 67 4 0 , 5 ? r o7 7 9 , 4 ? 0 7 + ? 7 2 10 7 0 , 0 1 ? r o0 0 0 , 0 1 ? 0 7 + ? n o i t i s o p r l a c i p y t w r o t h r o f e c n a t s i s e r k 0 1 ? ? ? ? ? p p d 0 00 7 0 , 0 1 ? r o0 0 0 , 0 1 ? 0 7 + ? 4 67 4 0 , 5 ? r o7 7 9 , 4 ? 0 7 + ? 6 2 19 4 1 ? r o9 7 ? 0 7 + ? 7 2 10 7 ? r o0 ? 0 7 + ?
cat5132 12 doc. no. 25092, rev. 01 ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice package outlines 10-lead msop
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 minipot catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 25092 revison: 01 issue date: 01/18/06 revision history date rev. reason 09/12/2005 00 initial issue 01/18/2006 01 update ordering information

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